Within a computer system there are generally three methods of data transfer between main memory or the registers of a central processing unit (CPU) and input/output (I/O) devices over a system bus. These three methods are programmed I/O, interrupt driven I/O, and direct memory access (DMA). With programmed I/O and interrupt driven I/O, the CPU is responsible for obtaining data from main memory for transfer to the I/O devices and for obtaining data from the I/O devices for transfer to main memory over the system bus. Thus, the programmed I/O and interrupt driven I/O requires the direct involvement of the CPU which ties it up managing the data transfer so that it can not otherwise perform other more important functions.
Direct memory access (DMA) was introduced which required a centralized DMA controller to alleviate the CPU involvement in data transfer. Centralized DMA control is well known. The centralized DMA controller essentially took over the role of transferring data over the system bus between main memory and I/O devices. In DMA accesses, the CPU involvement was reduced to the initial setting up of the DMA transfer and the clean up at the completion of the DMA transfer. While the actual DMA data transfer was being controlled by the DMA controller, the CPU could perform other computations or functions. As a result, DMA data transfer were more efficient than either programmed I/O or interrupt driven I/O methods. In order to avoid collisions on the system bus, the DMA control was centralized into a centralized DMA controller. The centralized DMA controller performed arbitration of the system bus to the attached I/O devices allowing only one at a time to be transferring data between it and the main memory. Furthermore, when multiple I/O devices desired to perform a DMA access simultaneously, the centralized DMA controller had to perform some prioritization method. As a result, the control logic of the centralized DMA controller can be rather complicated which can lead to a rather large block size for the circuitry of a centralized DMA controller.
Improved semiconductor manufacturing techniques have been shrinking the feature sizes in integrated circuits, such as transistor channel lengths. The smaller transistors have allowed more complicated integrated circuit chips to be constructed such that functional systems can now be formed within a single integrated circuit chip and produce satisfactory yields. These functional systems, which are substantially complete systems, are oftentimes referred to as a system on chip (SOC). In an SOC, there may be many functional blocks that require transferring data to or from a memory. Additionally, it is oftentimes desirable when constructing an SOC, to make it flexible so that the number of functional blocks can be expanded to handle more data and/or add other types of functional blocks. As the number of functional blocks increases, the potential arbitration problems may arise in an SOC. A disadvantage to using centralized DMA controller in this case is that the control logic may need to be redesigned to provide for the expansion.
Like reference numbers and designations in the drawings indicate like elements providing similar functionality. A letter after a reference designator number represents an instance of an element having the reference designator number.